Cost-Efficient Radiation Tolerance SRAM-based FPGA Development Methodology
Cost-Efficient Radiation Tolerance SRAM-based FPGA Development Methodology
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Abstract
Complex System-on-Chip (SoC) based on SRAM-based FPGAs are becoming increasingly attractive for use in space applications due to their reconfigurability and signal processing capabilities, as well as their increasing speed, capacity and low cost. Traditional SRAM-based FPGAs, however, are highly sensitive to the ionizing radiation environment in space, making them prone to radiation-induced upsets, which becomes an errors source that causes data errors or partial, full, temporal, permanent system interruption, however, the concurrency of customized chip housing -giving an additional protection against radiation effects- and space oriented development methodologies make SRAM-based FPGA technology suitable for space applications. To face this issue, there is available literature regarding mitigation techniques and fault-tolerance solutions; in most of cases it is based on partial or full -cold or hot- redundancy at several levels of development and implementation (RTL, chip, PCB modules...), however, applying these techniques is at cost of multiplying per x2 or x3 resources and significant increasing of power consumption, which could be difficult to implement into SoC/MPSoC technology regarding complex space applications. GENERA TECNOLOGIAS has designed, developed and verified -under an R&D space project- a Radiation Tolerance Methodology based on Single Event Effects (SEE) fault tolerance SRAM-based FPGA development techniques that reduce or avoided heavy redundancy needs. To ensure no errors and avoid error propagation in payload, techniques have been proposed to detect and correct SEE and some types of components of FPGA ecosystem have been replaced, avoided or reinforced. As result, we have obtained a Cost-Efficient FPGA Development Methodology alternative to radiation-hardened, heavy redundancy or antifuse FPGAs for non-critical space application such as satellite instruments, without unacceptably increasing the resources and power consumption of the system.
GENERA Soluciones Tecnológicas, S.L.
- Spain
admon@generatecnologias.es
The main objective of the experiment is to test, verify & validate in-orbit the developed "low-cost" radiation hardening techniques set by the usage of some FPGA cores implemented with this techniques set.
With the aim of testing and verify in orbit the developed methodology as much as possible, in the proposed work, we will adapt some of our previously developed IP-cores (based on this developed rad-tol methodology), measure, evaluate and compare the defined "Cost-Efficient Radiation Tolerance SRAM-based FPGA Development Methodology" for this Intel SRAM-based SoC with respect to radiation-induced upsets in orbit. A testbed using exchangeable experiments will be developed for this purpose and run on the Altera “5CSXFC6C6U23I7N” Cyclone V SX System-on-Chip (SoC).
Some third parties IP-cores like cores/experiments developed by third experimenters could be studied as part of our experiment to carry out, i.e. a joint experiment.
With regard to the results to be obtained, the testing results of the radiation hardening methodology will be improved as much as a high both usage of FPGA resources area and operational testing time are performed. Therefore, the both FPGA resources and testing time shall be as greater as possible.
a) On-board with regard FPGA-based HW resources:
We try to allocate at least about 70% of the FPGA resources for fulfilling the requirement of a wide area occupation regarding maximize the results from testing and verification & validation of the radiation hardening techniques set.
b) On-board with regard Core_ARM9-based SW resources: it will be close to standard image requirements.
c) On-ground: on ground resources will be close to standard image requirements.
d) Operational time: as much as possible.
The planning to develop the project is divided into chronologic milestones (MS), with the necessary time to fulfill each of them:
(Order / Milestones description / Deadline)
MS 0 - Kick off meeting day (T0)
MS 1 - OPS-SAT HW/SW Requirement Review (T0 + 2 weeks)
MS 2 - Detailed Design Review / Critical Design Review (T0 + 8 weeks )
- To define the exchangeable experiments/FPGA cores.
- To define HW/SW detailed design with respect to the specific testbed to process, measure, compare and FPGA fault-detection reporting.
MS 3 - FPGA/system Development (T0 + 16 weeks)
- To adapt the FPGA implementation-based selected functionality cores.
- To develop the testbed with regard to on-board hardware/software.
- To develop the on-ground TC/TM/Reporting software.
- Testing, V&V through simulation processes and integration inside SoC dev-board.
- Deployment support.
MS 4 - In-orbit Experimentation / Final test report (T0 + 24 weeks)
- Review the function of the general testbed in orbit.
- Monitor, control and review the function of the specific testbed in orbit.
- Final test reporting.
Eng. Francisco Pérez Bosch is expert in Reconfigurable On-Board Computing, High-Speed Interfaces, Process Control & Automation; and extensive knowledge hardware and software designs for critical systems with numerous related projects. Hardware engineer with 17 years of experience designing and developing digital/analog electronics, reconfigurable computing devices and communication protocols, for several sectors: military communications, teaching systems, nanotechnology and space. He got the title of BSc Telecommunication Engineering, from Universidad de Jaén, among the best of his class in 2004; and he co-founds GENERA Soluciones Tecnológicas, S.L. (GENERA Tecnologías) in 2009.
2009-now: CTO. Designer, developer and manufacturer:
- FPGA-based Communication Protocols: ECSS-CAN/CANopen, Telemetry & Telecommand Functions for Space Applications @ Research, Development and Innovation project.
- FPGA-based Acquisition Data and Control Electronics Card (TAD) for Atomic Force Microscopy (AFM) @ Research, Development and Innovation project for Nanotechnology.
- FPGA-based Software-Defined Radio (SDR) for Defense @ R&D project of Military Communications.
- Embedded Electronics cards based on FPGA, DSP and MPSoC technology for Aerospace-Defense Industry.
- SCADA, Control, Measurements and Telemetry Systems (Wonderware and LabVIEW based).
- VxWorks Real-Time OS and FPGA; developer, consultant and instructor.
- Real-Time & FPGA-based Test Benches and Machine Condition @ Manufacturing Industry.
@ GENERA Soluciones Tecnológicas, S.L.
2006-2011: Designed and developed the control and acquisition system for
- Robot of a 3D Physics System (EFAC);
- Hydroelectric Plant Hardware/Software Simulator (SCEC).
- Advanced SCADA and several computer control systems based on Labview.
- Electronics cards for valves control applications.
@ EDIBON International, S.A.
2004-2006: Designed the automated test plan for:
- Ruggered Computer for Swiss Defense Departments.
- And developed and integrated the automated test system for LINCE’s central computer (Spanish Defense Department’s main battle tank),
@ THALES Programas de Electrónica y Comunicaciones, S.A.
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The co-funding part is provided with GENERA's own funds.
Under an R&D space project (https://flightonchip.es/), our methodology (defined on the “MFOC-GEN-DD-001_0 DRAFT A - GENERA FPGA Implementation Methodology.pdf” document) have been developed based on following reference documents:
[1] “ECSS-Q-60-02A – ASIC and FPGA Development”, ECSS.
[2] “VHDL Modelling Guidelines, ASIC/001 Issue 1”, ESA ESTEC.
[3] “Radiation Impacts on Satellites due to GCRs and SEPs”, Mike Xapsos GSFC, Code 561, NASA.
[4] “SEU Mitigation Techniques for Advanced Reprogrammable FPGA in Space”, Department of Computer Science and Engineering - CHALMERS UNIVERSITY OF TECHNOLOGY Gothenburg, Sweden, FREDRIK BROSSER, EMIL MILH.
[5] “FAULT MANAGEMENT TECHNIQUES FOR SYSTEMS WITH SRAM-BASED FPGAS”, Universidad Politécnica de Madrid - Escuela Técnica Superior de Ingenieros de Telecomunicación, Ignacio Herrera Alzu.
[6] “High-Reliability FPGA-Based Systems: Space, High-Energy Physics, and Beyond”, IEEE.
[7] “Altera Quartus II Handbook Version 9.1 Volume 1: Design and Synthesis”, Altera, June 2010.
[8] Morgan Kaufman, “VHDL 2008: Just the New Stuff (Systems on Silicon)”, P. J. Ashenden and J. Lewis, ISBN-13 978-0123742490, 2007.
[9] J. Barnes, “High Integrity Software: The SPARK Approach to Safety and Security”, Addison Wesley, ISBN-13: 978-0321136169, March 2003.
[10] D. Chen, J. Cong, Y. Fan, “Low-Power High-Level Synthesis for FPGA Architectures”, Proceedings of the 2003 International Symposium on Low power electronics and design, pp. 134-139, 2003.
[11] Design Abstraction Ltd., “Common HDL Design Errors”, June 2010.
[12] J. M. Emmert, C. E. Stroud, B. Skaggs, M. Abramovici; "Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration," Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 165-174, 2000.
[13] J. Hammarberg and S. Nadjm-Tehrani, “Development of Safety-Critical Reconfigurable Hardware with Esterel”, Electronic Notes in Theoretical Computer Science, vol. 80, pp. 219-234, 2003.
[14] R. E. Harr, A. G. Stanculescu, “Applications of VHDL to circuit design”, Springer, ISBN-13 978-0792391531, 1991.
[15] IEEE, “1076-2008 IEEE Standard VHDL Language Reference Manual”, IEEE, Jan 2009.
[16] J Willis, Z. Li, T. Lin, “Use of embedded scheduling to compile VHDL for effective parallel simulation”, Proceedings of the conference on European design automation, pp 400-405, 1995.
[17] D Mills, C.E. Cummings, “RTL Coding Styles That Yield Simulation and Synthesis Mismatches”, Proceedings of SNUG 99, 1999.
[18] Motor Industry Software Reliability Association, “Guidelines for the Use of the C Language in Critical Systems”, MIRA, ISBN 0 9524156 2 3 paperback, October 2004.
[19] RTCA/EUROCAE, DO-254 "Design Assurance Guidance for Airborne Electronic Hardware", RTCA, 2000.
[20] ISO, "Information Technology — Programming Languages — Guidance to Avoiding Vulnerabilities in Programming Languages through Language Selection and Use – DRAFT”, 2009.
This idea could address indirectly any ESA mission or activity that includes FPGA technology. Thank to capacities offered by OPSSAT, a rad-tol FPGA development methodology may be verified and improved in orbit.
2nd Round idea
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- May 20, 2021
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